module tb_daptive_filter;
parameter length = 16;

reg clk;
reg rst_n;
reg signed [length-1:0] input_signal;
reg signed [length-1:0] expect_result;
wire signed [2*length+4:0] parallel_compressor_out;


adptive_filter
	#(length)
	adptive_filter_u0
	(
		.clk 						(clk 						),
		.rst_n      				(rst_n 						),
		.input_signal				(input_signal				),
		.expect_result				(expect_result				),
		.parallel_compressor_out	(parallel_compressor_out	)			
	);

always #5 clk = ~clk;

initial begin
	clk = 0;
	rst_n = 0;
	#150
	rst_n = 1;
end

initial	begin
	$monitor($realtime,"\t%b\t%b\t%d", input_signal,expect_result,parallel_compressor_out);
end


wire rst_write;
wire signed [2*length+4:0] write_signal;
assign write_signal = parallel_compressor_out;   
assign rst_write = clk & (rst_n);//产生写入时钟信号，复位状态时不写入数据

//get the excitation
integer Pattern;
parameter data_num = 5000;
reg [length-1:0] stimulus[1:data_num];
initial
begin  
	$readmemb("D:\\Document\\Code\\Verilog\\adaptive-filter\\signal\\excitation_signal.txt",stimulus);
	Pattern=0;
	input_signal=0;
	forever
	begin
		@(posedge rst_write);
		if (Pattern == data_num) begin
			Pattern = 1;
		end
		else begin
			Pattern = Pattern + 1;
		end
		input_signal=stimulus[Pattern];
	end
end


//expect signal
integer index;
reg [2*length+4:0] expect_signal_mem [1:data_num];
initial begin
	$readmemb("D:\\Document\\Code\\Verilog\\adaptive-filter\\signal\\expect_signal.txt",expect_signal_mem);
	expect_result = 0;
	index = 0;
	forever
	begin
		@(posedge rst_write);
		if (index == data_num) begin
			index = 1;
		end
		else begin
			index = index + 1;
		end
		expect_result = expect_signal_mem[index];
		//$display("%b",din);
	end
end


//将仿真数据dout写入外部TXT文件中(Response_Signal.txt)
integer file_out;
initial
begin
  //文件放置在工程目录路径下                                                  
	file_out = $fopen("D:\\Document\\Code\\Verilog\\adaptive-filter\\signal\\response_signal.txt","w");
	if(!file_out)
		begin
			$display("could not open file!");
			$finish;
		end
	#800000 $fclose(file_out);
end


always @(posedge rst_write )
	begin
		casex(write_signal)
			1'dx:;
			default:$fdisplay(file_out,"%d",write_signal);
		endcase
	end


endmodule